Design and Analysis of Approximate Multipliers using Approximate 4:2 Compressors

Approximate computing techniques have emerged as a promising approach to enhance efficiency by sacrificing a bit of accuracy. Within this framework, approximate multipliers have gained significant attention for their ability to find a sweet spot between precision, performance, and power efficiency. One popular method for creating these multipliers involves using 4:2 approximate compressors, which act as efficient components in approximate arithmetic circuits. This paper introduces two different designs for 4:2 approximate compressors, which are then utilized to deliberately decrease the accuracy of the multiplier while achieving substantial gains in power efficiency and speed. The effectiveness of these proposed designs has been confirmed through simulations using the Genus software, demonstrating a noteworthy 30% and 34% reduction in the required area and a 42% and 44% reduction in power consumption.