Design of High-Speed Pipelined 1024Point Radix-2ˆ2 Fft Using Modified Input Scheduling Algorithm

FFT algorithms using hybrid Radix structures play a key role in the design of DSP processors used in 4G and 5G communications. This paper explores a low complex and high speed hybrid FFT structure namely Radix-2ˆ2 that harmonioulsy blends the merits of both Radix-2 Radix-4 structures. The proposed design uses a modified scheduling algorithm requiring less hardware elements and also resulting in a fixed delay in the commutator. The design occupied an area of 33271.2µm
²
and could operate upto a frequency of 92.6MHz with a power dissipation of 2.299µW in 90nm gpdk technology.