Error Resilient Approximate Restoring Divider for Image Processing Application

The number of transistors and the complexity of the circuits both rise as Very Large-Scale Integration (VLSI) technology progresses, which leads to an increase in the amount of power that is required. Due to the wave borrow subtraction that occurs in each row of partial remainder computation, division is a more complicated mathematical operation than addition or multiplication. Computing by approximation is gradually becoming the norm for producing compact, economical, and high-speed solutions, particularly in architectures that are tolerant of mistakes to some level. As a result of the persistence of vision, even minute differences in the results of image and video processing apps go undetected. As a result, applications of this kind provide the optimal setting in which to put approximation computing into practice. The image division application is going to be performed using a 16/8 division module, which is proposed in this study. Approximate Divider Cell ADC1, ADC2, ADC3 and ADC4 are modified versions of the actual cell that makes up the division module. This was done in order to minimize the space and power consumption of the overall design. ADC1, ADC2, ADC3 and ADC4 show area and power improvement of (23.82%, 19.68), (17.41%, 48.56%), (26.82%, 48.88%) and (13.03%, 14.36%) respectively, for approximation factor 8, when compared to exact restoring divider.