Comparative Analysis of CMOS Schmitt Triggers

This paper presents the performance analysis of various CMOS Schmitt triggers which are used in the VLSI industry for noise reduction. A comparative analysis of different CMOS Schmitt trigger designs has been provided. The design along with the working principle for each Schmitt trigger architecture is discussed. At last comparison between all the architectures with respect to parameters like hysteresis width, power and delay is shown. It is shown that a single architecture may not be able to meet all the specification needs. So, a comparative study has been done for some of the widely used architectures in GPIO buffers. So that depending on the requirement, designer can decide which design architecture to proceed with. All the simulations were implemented using CADENCE Virtuoso in Spectre simulator using 500nm CMOS technology.