Design and Validation of Domino CMOS D Flip Flop at 16nm Regime

The relentless pursuit of higher performance and energy-efficient integrated circuits has led to significant advancements in semiconductor technology. At the forefront of this progress is the 16nm CMOS process node, offering increased transistor density and enhanced circuitry performance. This study presents the design and validation of a high-performance Domino CMOS D Flip Flop, tailored for operation at the cutting-edge 16nm technology node. Initially, this work presents the design of a CMOS AND gate and a domino AND gate at contrasting micro scales. Comparing the CMOS AND gate with the domino AND in terms of size and power consumption reveals significant differences in performance. Then, proposed the Domino CMOS D flip flop which leverages the advantages of dynamic logic to achieve faster operation while minimizing power consumption. The simulation results reveal that compared to traditional methods the domino-based design resulted in less power dissipation and high speed with minimum number of transistors.