Performance Analysis of a New Low Power BIST Technique in VLSI Circuit by Reducing the Input Vectors

VLSI circuit testing is complex and costs over 30% of the total IC design. The built-in self-testing technique is popular for its extensive fault coverage and efficiency. BIST refers to a hardware device testing construction used to perform fault detection and improve the device's performance to ensure a fault- free environment to avoid causing damage within the device's lifetime. As ICs are getting more complex day by day, different BIST modules are needed to test different circuits, which increase complication in design. As a result, power consumption and clock cycle increase. This research introduces a new Built-in Self-Test (BIST) technique for VLSI circuits. To deal with the shortcomings of conventional techniques, a BIST technique is proposed, which can test the circuit's functionality and detect faults successfully. The proposed model has been implemented using 22nm PTM model by employing LTSpice simulation software. The proposed model decreases power consumption upto 47.54% in without fault, 45.34% in open circuit fault and 45.63% in short circuit fault conditions compared to conventional technique and reduces the input vectors which in turn minimizes design intricacy and ensures an improved and novel approach for self-testing compared to many other existing BIST techniques.