Efficient Repair Configuration Algorithm, for Improving Yield of Semiconductor Memories

As CMOS technology scales into nanometer range, the density of the embedded memory in a chip increases. Due to high metal electron migration current flowing per unit area, and due to aging effects, like Hot Carrier Injection (HCI) and Negative-Bias Temperature Instability (NBTI), a soft fault can occur later in the lifespan of a System on Chip (SOC). Increased on-chip memory density and increased defect density requires both redundant rows and columns that can be reconfigured to replace faulty rows or columns. Factory repair using Self-Test and Repair increases yield, and field repair also extends the lifespan of a chip by automatically testing and intelligently re-configuring the available spare whenever a failure is in the life span of a chip. This paper presents an algorithm to efficiently use row and column redundancy for faults in different types of memory. The proposed algorithm achieves an increase of 10% in repair-ability of SRAM array as compared to existing methods.