A Second-Order Noise-Shaping SAR ADC With Passive Integrator and Active Amplifier

The paper introduces a novel second-order noise-shaping circuit structure for designing high-resolution and low-power consumption Noise-Shaping Successive Approximation Register (NS SAR) Analog-to-Digital Converters (ADCs). This circuit utilizes an amplifier with a gain of 5 and two passive integrators to enhance the in-band noise attenuation through second-order noise shaping. The paper also investigates the impact of gain error in the dynamic amplifier on the resolution of the ADC. By achieving a Signal-to-Noise and Distortion Ratio (SNDR) of 92.9 dB peak across a bandwidth of 0.5 MHz, the effectiveness of the proposed circuit structure is verified. Overall, this research presents a promising approach for designing NS SAR ADCs with improved resolution and reduced power consumption, offering potential benefits in various applications that require high-performance analog-to-digital conversion.