Silicon-Based Integrated True-Time Delay Line with Adjustable Large Delays

In this work, we design, manufacture and package a large delay adjustable silicon-based true-time delay line chip. Specifically, we focused on evaluating the performance of a single switch within the chip. Meanwhile, in order to ensure efficient and accurate measurement of the switching state voltage while mitigating the impact of state voltage drift, we devise a semi-automatic scanning program, which facilitates the precise acquisition of the switching state voltage over an extended period. The chip showcases impressive features, including a substantial delay step of 20 ps and a maximum delay time of 2.54 ns. Moreover, it exhibits commendable signal transmission capabilities, with a clear and observable eye diagram shape at 30Gbps under a 2
⁵¹
–1 pseudo-random bit sequence (PRBS) signal. Furthermore, we find that the power penalty difference between the longest and shortest signal paths is minimal, measuring only 0.1686 dB.