Hybrid-Domain In-Memory Polynomial Acceleration based on 40nm RRAM Multi-Core Chip for Machine Vision Calibration

For the first time, a novel hybrid-domain (time, analog, and digital) in-memory polynomial computing is proposed and experimentally demonstrated using a RRAM-based expandable ternary multiplier (ETM) to accelerate polynomial transformation (PT) algorithms. The ETM is constructed based on 1T1R cell, which subtly implements multiplication of two multibit signed operands by orchestrating the inputs on the word lines (time-domain sequence) and bit lines (analog voltage-domain) to enable ternary multiplication (TM). The subsequent accumulation is completed through peripheral shift-adder (digital-domain). A 40nm RRAM chip with 30 integrated four-quadrant TM arrays are designed and implemented to realize high-order parallel matrix-vector computation and PT acceleration through synthesizing the hybrid-domain in-memory polynomial computation, demonstrating software-comparable calibration of lens distortion in machine vision applications with high calibration throughput (158Mpixels/s) and energy-efficiency (3.81Gpixels/W).