FPGA Implementation of MAC Unit for Artificial Neural Network Accelerators

In recent years, Neural Networks (NNs) have revolutionized business and daily life, it has entered many industrial applications, including Computer Vision and Healthcare. Software implementation of NN offers poor performance. Therefore, most real-time applications require hardware implementation. The main building block of the NN is a Multiply-Accumulate Operation (MAC). This article introduces design exploration and the FPGA implementation of parametrized floating point 64/32-bit MAC. In addition, the design of the multiplier has been improved to improve performance by building a tree of partial products. Therefore, the proposed 32-bit floating-point MAC unit has significant improvements 514 out of 32070 logic utilization with total pins around 98 out of 457 and a maximum frequency of 46.23MHz. Consequently, this study would have a major impact on developing and prototyping future efficient neural network hardware accelerators.