Optimal Implementation of the Boxfilter Algorithm Based on Feiteng Platform

The Boxfiltering algorithm is a linear filtering algorithm commonly used in image preprocessing. It is widely employed in the field of image processing due to its ability to effectively remove noise while preserving the original detailed features of the image. With the advancement of domestic high-performance digital signal processors in the Feiteng series, there is an urgent need to adapt and optimize high-performance image processing algorithms for the Feiteng DSP architecture. To address these issues, this study focuses on the vector parallel optimization of the box filter algorithm based on the FT-M7002 platform. The box filter parallel algorithm is implemented utilizing the vector operation unit of the FT-M7002 platform and the SIMD instruction set embedded in the compiler. Moreover, a type conversion interface between character type and floating-point type is designed and implemented to enhance platform scalability. Tail loop processing is employed to tackle the issue of insufficient filling of parallel computing units and maximize the utilization of the vector computing resources of the FT-M7002 platform. The performance of the optimized algorithms is compared and analyzed under various convolution kernels and image scales. The results indicate that compared to the serial algorithm, the optimized algorithm achieves an acceleration effect of 1.806 to 3.036 times. Furthermore, when compared to the algorithm performance of the TMS320C6678 processor, the optimized algorithm based on the FT-M7002 platform achieves an acceleration effect of 3.479 to 4.056 times.