FORSA: Exploiting Filter Ordering to Reduce Switching Activity for Low Power CNNs

Switching activity in digital circuits depends on the temporal distribution of the data participating in the operation which directly influences the interconnect, dynamic power and timing of the system. This paper proposes an efficient method for reducing both power and latency of matrix-multiplication operations found in many applications such as convolution neural networks (CNNs). The approach takes advantage of the unique characteristics of CNN with input stationary for efficient multiply-add operations. Since most applications use reduced accuracy for MAC, the proposed work assumed 8-bit fixed-point representation for different quantization levels. As a demonstrator, CIFAR-10 data set has been used for end-to-end analysis of the filters on a 3-ConV with 2-FC CNN model structure. The filters' were re-ordered to reduce the switching behaviour between successive weight fetching. This directly impacts the dynamic power consumption and provides an estimation of 20.62% less classification power with 5-bits for quantization levels and 8-bit fixed-point representation for the MATLAB CNN pipeline. While with the full digital implementation, ~11.43 % reduction is achieved. The difference could be due to the internal power of the cell or the arrival times of the signals. Moreover, reduced switching activity leads to reduced interconnect power which is normally high compared to computing.