Many-Core Display Stream Compression Decoders With Simplified Pixel Prediction

The Video Electronics Standards Association (VESA) Display Stream Compression (DSC) video codec has been widely accepted to compress video streams over display links. This paper presents three many-core software DSC decoder implementations which utilize fine-grained task-level parallelism and are implemented with 65–265 processor cores and 2–6 memory modules. The designs achieve reduced complexity and increased energy efficiency by supporting modified medianadaptive prediction (MMAP) and midpoint prediction (MPP) to predict pixel values, but not the optional block prediction (BP), which causes minor degradation of rendered quality on only certain image types. The implementations achieve up to 24–96 1080p frames per second at 1.1 V and 1.75 GHz, and as low as 8.4 nJ per 4:2:0 pixel at 0.76 V and 678 MHz. Compared to the many-core DSC decoders that support BP, the proposed decoders occupy 1.32-1.33x smaller chip area, achieve 1.33-1.34x higher throughput per area and 1.25-1.29x lower energy per pixel.