A Technology/Circuit Co-design Framework for Emerging Reconfigurable Devices

Reconfigurable devices are gaining increasing attention as a viable alternative and complementary solution to the prevalent CMOS technology. In this paper, we develop a device and circuit-level co-design framework for evaluating and exploring the performance of emerging reconfigurable devices. We use reconfigurable FET as a case study by creating a cell library and performing logic synthesis and physical design to investigate the impact of device-level parameters, such as supply voltage and nanowire diameter, on the circuit-level performance. Results show that optimal device-level parameters exist, whose values are highly dependent on the overall circuit-level performance, such as energy, delay, area, or energy-delay-area product.