A 3.97 µW 11.2b 500 kS/s Hybrid SAR ADC via Time-Mode Signal Processing

This paper presents a 12b hybrid ADC consisting of a 8b successive approximation register (SAR) analog-to-digital converter (ADC) with top-plate sampling, a variable-slope voltage-to-time converter with built-in absolute-value function, and a 3-stage cyclic gated Vernier TDC. The proposed ADC features the ability to accommodate a large input without sacrificing linearity, low power consumption, and technology compatibility. A number of techniques are proposed to improve performance and power efficiency of the ADC. These techniques include a sub-threshold delay-locked loop with pulsed control signals for clock generation, clock kickback reduction to minimize kickback and mismatch induced sensitivity loss of the comparator of the SAR ADC, a gated cyclic Vernier TDC to minimize the resolution loss caused by the improper injection of time inputs and a virtually unlimited dynamic range, a self-resetting arbiter with zero metastability window to improve the resolution of Vernier TDC, and a significantly simplified synchronous SAR for a better power/area efficiency. The ADC is designed in a TSMC 130 nm 1.2 V CMOS technology with a reduced supply voltage of 0.8 V and analyzed using Spectre with BSIM3.3 device models. Simulation results show that at 500 kS/s, the ADC offers a SNDR of 69.04 dB and ENOB of 11.17 while consuming 3.70 µW, yielding a Walden FOM of 3.21 fJ/conv.