An Analog-to-Information Architecture for Single-Chip Sensor-Processor Inference System

Compressed sensing (CS) establishes that signals fulfilling certain conditions can be sampled at a much lower rate than that defined by the Nyquist-Shannon sampling theorem while still keeping most information. Therefore, the monolithic implementation of CS is notably interesting for different applications. By its very nature, CS encodes global information of the sampled signal and hence compressed samples can be used for inference purposes. Thus, a particular application of CS is the implementation of inference in the compressed domain, i.e., without reconstructing the compressed signal. In this paper, we present an analog-to-information CS-based architecture for on-chip inference. The performance of the proposed architecture has been evaluated using facial recognition as a case study for different scenarios with varying lighting, expression, and occlusion conditions. Different mixed-signal hardware building blocks are also presented. These building blocks have been designed in the 110 nm LFoundry technology.