Study of parametric variations on Heterojunction Dual Gate Vertical TFET for performance Enhancement

TFET’s are considered as the next generation of ultra-low power semiconductor devices. However, to make them commercially viable, it is necessary to reduce the leakage current, ambipolar current (I
amb
) and enhance the on current (I
on
) caused by the tunnelling. To address these technological challenges, a unique double-gate vertical TFET has been proposed in this study, and Technology computer-aided design (TCAD) simulation is used to examine its electrical properties. In this paper we have investigated all parametric variations to enhance the on current and to improve the Drain induced barrier thinning (DIBT) and Subthreshold Swing (SS). I
on
/I
off
ratio of 10
⁸
, SS of 36 mV/dec, DIBT of 8 mV/V, and 6 fF gate to drain capacitance have been achieved. The results reveal that the double-gate TFET outperforms the ordinary single gate TFET in terms of on current (I
on
), DIBT and gate to drain capacitance (C
gd
).