Design of Clock Multiplier using Modified Voltage-controlled Delay Line

In the presented paper, a pioneering voltage- controlled delay line (VCDL) and edge combiner (EC) design have been introduced, showcasing their prowess in 90nm Cadence Virtuoso. This innovative solution operates effectively at a 1.8V supply voltage, delivering exceptional performance at a frequency of 125MHz. The EC, a key component, adeptly merges the eight clock phases generated by the VCDL, resulting in an impressive output signal that surges to four times the reference frequency, reaching a formidable 500MHz. Unlike conventional phase-locked loops (PLLs), which grapple with limited VCO noise suppression bandwidth, this VCDL design offers a significantly broader control voltage range, spanning from 0 to 1.3V. This expansive voltage variation enables the unit delay time to flexibly range from a swift 0.263ns to a measured 1.606ns at the 125MHz mark. Furthermore, meticulous power consumption analysis reveals that each VCDL stage exhibits frugal energy consumption, drawing a mere 58.56µW. Meanwhile, the EC operates efficiently at the same frequency, consuming 1.595mW. This innovative design approach not only enhances noise performance but also provides a versatile VCDL solution applicable to a wide array of scenarios.