4H-SiC Trench MOSFET with Half-Surrounded Gate for Improved Gate Oxide Reliability

In this work, a novel silicon carbide (SiC) trench metal- oxide-semiconductor field transistor (MOSFET) with half- surrounded gate (HSG-TMOS) is proposed and its performance is studied via numerical simulation with Silvaco TCAD. The gate trench of the HSG-TMOS is half surrounded by two p-type epitaxial layers. The lightly doped Pbase region can alleviate the conduction characteristic degradation caused by the L-shaped current channel while the heavily doped p- type shield region (P+SLD) shows great shielding effect in the blocking state. Therefore, the blocking characteristic is significantly improved and the peak electric field in the gate oxide (E
ox,peak
) is relieved. Simulation results show that compared with the trench MOSFET with a P+SLD under the gate trench (GP-TMOS), the breakdown voltage (BV) and Baliga's figure of merit (BFOM) of the HSG-TMOS increases by 46.0% and 14.9%, respectively. The E
ox,peak
at the drain bias of 1200V decreases from 2.75MV/cm for the GP-TMOS to 1.90MV/cm for the HSG-TMOS. It decreases by 30.9%, which improves the gate oxide reliability, significantly. In addition, the switching power loss of the HSG-TMOS is 48.6% lower than that of the GP-TMOS due to the reduced specific capacitance. Moreover, the influence of the key parameters on the HSG-TMOS is discussed.