A novel double PN-junction Isolation Substrate for Isolating High and Low Side HEMTs in Half-bridge Integrated Circuits

In conventional monolithic integrated half-bridge circuits, the High Side (HS) High Electron Mobility Transistor (HEMT) and Low Side (LS) HEMT can experience mutual interference due to differing substrate potentials. While existing single PN-junction isolation structures have demonstrated effective isolation capabilities, ensuring this isolation typically necessitates the connection of the substrate to Vin, which poses challenges in terms of packaging and heat dissipation. This paper builds upon the foundation of single PN-junction isolation substrate structures and introduces a novel Double PN-junction Isolation Substrate (DJIS) structure. Sentaurus TCAD simulations have substantiated the positive correlation between trench depth and substrate breakdown voltage. The assessment of the isolation performance of DJIS is based on the observation of the impact of different VSW on threshold voltage shifts. It indicate that the DJIS structure ensures robust withstand voltage and isolation capabilities, whether the substrate potential is grounded or connected to Vin. Moreover, the incorporation of a P+ Si layer at the bottom enhances the elastic modulus and hardness of DJIS, thus elevating the device's reliability. The structure proposed in this paper offers a fresh perspective for achieving isolation in monolithic integrated half-bridge circuits.