Simulation Study of p-GaN Gate HEMTs With Dielectric Interlayer

In this work, we present a p-GaN gate HEMT with a thin dielectric interlayer and investigate the impacts of interlayer on the performances of p-GaN gate HEMTs using Silvaco TCAD. The transfer characteristics and gate forward breakdown characteristics are simulated, and the results show that devices with interlayers exhibit a smaller gate leakage and a much higher gate forward breakdown voltage (V
G-BD
) compared to the conventional p-GaN gate HEMT. The V
G-BD
of devices with 3 nm Al
2
O
3
, HfO
2
and SiN interlayers represent 145%, 79% and 97% increase (@ I
G
= 1μA/mm), respectively.