Systematic Error Compensation in a Unary Segment of a 10-bit Current-Steering DAC

Experimental results for a segmented digital-to-analog converter (DAC) are presented showing an integral nonlinearity (INL) reduction with help of switching schemes. Based on previously published simulation results, four switching schemes have been selected for the experiment. A 10-bit segmented current-steering DAC has been designed in X-FAB 180-nm SOI technology. The designed Multi-Scheme Unary Decoder allows implementing the selected switching schemes that control the same array of elements. According to the simulation results, one of the gradient-optimized switching schemes has promised the INL reduction but this has not been confirmed in the experiment. Therefore, corrections of the approach for processing the simulation results are derived. Among switching schemes, the Reshuffled Diagonal Rotated Walk (RDRW) switching scheme confirms the best INL reduction. Based on the experimental results, systematic error profiles have been reconstructed and their parameters have been calculated. Obtained data have shown that the systematic error is joint, anisotropic and rotated. The linear component is about 10 times larger than the quadratic one. The contribution of the 3
^rd
order component is negligible. Recommendations for a function-level simulation of switching schemes are given.