Switching Sequence Reordering by Foreground Self-Calibration Circuit in DACs

This paper describes the implementation of foreground self-calibration circuit for the switching-based calibration method for 8-bit unary current-steering segment. The design of the circuit is discussed on the functional level, as well as the internal blocks of the circuit. The mathematical model was developed in MATLAB and the Verilog description of the design was obtained. Finally, the RTL description for the design is synthesized for a 90 nm technology. The clock frequency is 320 MHz, the number of logic gates is 45k.