A Speed Up Method towards DDR Subsystem Functional Verification in SoC

As CMOS technology is approaching atomic feature size, the complexity of SoC (System on Chip) is increasing. As a result, the SoC verification is facing increased challenges, which calls for the development of a new system-level verification methodology. En route to system-level verifications for SoCs, an efficient method for speeding up the SoC verification is the main desideratum. To this end, this paper proposes an efficient method for speeding up subsystem-level functional verification, and takes DDR subsystem in a SoC design as an example to validate the proposed method. A bypass skill is utilized in the speeding up method. Through replacing the DDR configuration interface (a DDR AHB bus connecting to CPU) with another faster designed AHB bus, the proposed speeding up technique takes advantage of a series of tasks within the designed initialization master, which are faster than the same operations which are issued from CPU. The experimental results show that our proposed speeding up approach is efficient, and the running time speed up ratios reach 7.0×, 6.8×, 11.6× for RTL-level simulations, gate-level simulations without back-annotation, and gate-level simulations with back-annotation, respectively.