Behavior Simulation of CDR for SSC System With a Compact Quarter-Rate Linear Phase Detector

In this paper, we give analysis and comparison for conventional DLL-based CDR and proposed quarter-rate PI DLL-based CDR for spread-spectrum clocking (SSC) interfaces, respectively. Through theoretical analysis, we observe that the steady-state phase error of conventional approaches to infinity while the steady-state phase error approaches to a constant in the proposed CDR. Since the steady-state phase error results in phase offset for CDR to sample data, the proposed CDR can provide an incentive design for SSC applications. To improve jitter tolerance, we stabilize the system by adding integrators and zero points to enhance the phase-tracking ability. Operating at 3-Gb/s data with the SSC profile of 95-kHz modulation frequency and ±5% triangular-shape modulation rate, the CDR was design with loop bandwidth of 4.8 MHz and phase margin of 55 degrees.