A Spike-Sorting-Assisted Compressed Sensing Processor for High-Density Neural Interfaces

Brain science research requires high-density neural interfaces, where data transmission is challenging in limited power budget. Compressed sensing is a promising approach to reduce data rate of the spike signal, yet the quality of the reconstructed signal greatly depends on the selection of sensing matrix. This paper proposes a spike-sorting-assisted compressed sensing method that exploits using different sensing matrices according to the cluster classes of spikes. The simulated classification accuracy of the proposed method shows a maximum improvement of 20%, i.e., from 70% to 90%. The average classification accuracy achieves 96.26% and 93.34% at a compression ratio of 8 and 16, respectively. Implemented in a 65 nm CMOS process, the proposed processor occupies a core area of 0.073 mm
²
. The simulated power consumption is 0.931 μW while powered by 0.9 V supply and operating at 24 kHz.