High-throughput PIM (Processing in-Memory) for DRAM using Bank-level Pipelined Architecture

Artificial intelligence (AI) is a technology requires massive computation. Among many solutions that accelerate AI for faster computation and low power, processing-in-memory (PIM) is a promising candidate. In this paper, we propose a PIM architecture of DRAM via custom pipelining. Our architecture proposes pipelining of operation units that leads to massive throughput, where an operation unit consists of eight banks. Our optimized pipelined architecture shows a -19.16% reduction in power-delay-product (PDP) per area and 24.1% better throughput compared to the latest DRAM PIM architecture with only 0.7% area overhead.