Optimizing Timing for Multi-bit Flip-Flop Intensive Designs Compatible with Commercial EDA Flow

The primary reason of using multi-bit flip-flop (MBFF) cells as opposed to using single-bit flip-flop (SBFF) cells is to save the dynamic power consumed in the clock network as well as in the flip-flops. However, such power saving comes at the cost of losing the flexibility of moving internal individual flip-flop components over the die, which inevitably negatively affects timing optimization. This work overcomes this inherent limitation by proposing three new design flows, which are fully compatible with commercial EDA (electronic design automation) flow: (flow 1) generating MBFF cells with mixed directions of flip-flops’ D-to-Q flow and including them in cell library, (flow 2) splitting MBFFs into smaller ones to relax cell movement, so that timing can be improved, and (flow 3) applying flow 1 in the placement stage followed by applying flow 2. Through experiments with a set of benchmark circuits, it is shown that our proposed flows 1, 2, and 3 are able to reduce the amount of total negative slack by 10%, 14%, and 23%, respectively at the expense of a small increase of power consumption over that produced by the commercial EDA flow.