A Small Area Cyclic Vernier Delay Line TDC Based ADDLL using Linear Delay Inverter

A small area cyclic vernier delay line time-to-digital converter (TDC) based all digital delay-locked loop (ADDLL) is presented in this paper. The TDC shares coarse and fine TDC stages of the two-stage TDC and the TDC stages are vernier delay line that consists of proposed digitally controlled linear delay inverter for high resolution and area reduction. After TDC operation, clks locked to below coarse resolution are selected by 32 to 1 mux and transferred to one fine delay stage that has 16-step linear delay resolution. Fine delay lock operation is done using encoded TDC code. The proposed DLL circuit works with Samsung 2S nm CMOS process. The supply voltage of the DLL is 1.0 V and the power consumption at 2 GHz is 9.76 mW. The total size of the layout is 0.00684 m$\mathrm{m}^{2}$. The resolution is 1.8 ps and frequency range is 1.2-2 GHz.