Allocation of Multi-bit Flip-Flops Targeting Low-Power Chips

Using multi-bit flip-flops (MBFFs) becomes one of the key ingredients in industry for reducing dynamic power consumed by the flip-flops and clock network. On the other side, the commercial EDA (electronic design automation) flow conventionally optimizes the circuit timing with a higher priority over the power since meeting the timing constraints is utmost important. One core technique of timing optimization used in the EDA flow is properly sizing the cell instances including flip-flop cells i.e., updating cells’ output driving strength in circuit. However, such up/down sizing on flip-flop cells hinders a full flexibility of allocating MBFF cells, thereby saving less power since flip-flops with different driving strengths cannot be grouped together for an MBFF allocation. This work overcomes this limitation, targeting low-power chips. Precisely, we propose two new design flows: (flow 1) sizing cell instances, but retaining every flip-flop in circuit to be the weakest driving strength, then grouping flip-flops for MBFF allocation; (flow 2) generating MBFF layouts with mixed driving strengths and including them in cell library, so that EDA tool is able to suitably map MBFF cells with less power while meeting circuit timing. Through experiments with benchmark circuits, it is shown that our proposed flows 1 and 2 are able to produce circuit implementations with 0.42% and 4.34% less power consumption over that produced by the conventional EDA flow.