Regression Analysis Based Circuit Power Estimation Technique

Recent advances in Very Large Scale Integration technology(VLSI) enable the integration of millions of transistors on a single chip. Early power estimation is essential in VLSI circuits because it greatly impacts the reliability of VLSI circuits. Therefore, signal statistics obtained from functional simulations can be used to perform behavioral-level performance estimation and calculate energy consumption. Accuracy and efficiency of power estimation technique is always have trade-off. Power consumption of VLSI circuits can be reduced by properly estimating power during design phase. This has greatly increased circuit complexity, resulting in a need for power estimation techniques that are time-saving and cost-effective. High-level power estimation has many advantages over low-level abstraction power estimation techniques. This reduces both time constraints and computational resource requirements. Among the training functions assessed, 'traingd' emerges as the most fitting choice for power estimation in combinational circuits. The experimental results shows that proposed method has minimal deviation from the ideal power estimation, with deviations of only 0.77% and 1.04% observed. Specifically, for NAND circuits, the Root Mean Square Error (RMSE) stands at 0.0341, accompanied by a correlation coefficient (R) of 0.960. Similarly, in the case of NOR circuits, the RMSE and R values are 0.0387 and 0.973, respectively. Regression analysis using Back Propagation Neural Network is an attractive tool for solving complex, nonlinear and time-constrained problems and is therefore suitable for power estimation in CMOS VLSI circuits.