Effect of Transistor Sizing on Noise Margin Enlargement of Ternary Gates

Ternary logic offers the ability to boost computational performance while requiring fewer interconnections. Despite the benefit, ternary logic is less noise tolerant than binary logic. As a result, it is critical to carefully evaluate noise margin in ternary logic to provide acceptable circuit reliability. The research work focuses on the noise margin of proposed transistor sizing for Ternary NAND and NOR gates to provide uniformly wide noise margin values with improved power consumption and PDP. The noise margin of CNTFET based ternary gates is calculated and examined using VTC. Circuits are analysed on the HSPICE simulator with the help of DC sweep analysis. The simulation shows that the proposed transistor sizing can increase static noise margin up to 58%. The results states that sharpness, steepness and equal distribution of NMs are important factor for lower noise sensitivity.