A Cost-Effective FPGA-Based Approximate Multiplier for Machine Learning Acceleration

This paper introduces a novel approximate multiplier tailored for FPGAs, with a primary focus on its application in hardware accelerators for deep machine learning computations. In deep learning, multipliers represent a substantial portion of the hardware complexity. The primary objective is to enhance hardware efficiency compared to exact multipliers while maintaining an acceptable level of accuracy, especially for inference tasks. The proposed multiplier employs a parallel architecture featuring a configurable set of approximate adders. The paper provides comprehensive insights into the design of both INT8 and UINT8 configurations of this multiplier. The evaluations encompass error analysis findings, hardware implementation results, and accuracy measurements for the inference of a selected set of benchmark deep learning models. The results illustrate that a chosen configuration of this multiplier can achieve a notable 9% reduction in overall LUT utilization while incurring only an average 0.28% and 0.06% reduction in inference accuracy before and after approximation-aware retraining, respectively.