Hardware-Based Acceleration of an Approximate 2D DCT for a System-on-Chip

This paper presents a hardware-based acceleration method for computing an approximate two-dimensional discrete cosine transform (2D DCT) within a system-on-chip (SoC) The technique employs a pipelined architecture written in the Verilog hardware description language and synthesized on a field program gate array (FPGA) SoC platform. To test the proposed architecture, we integrate the system as a memory-mapped peripheral of a Dual Core Cortex A9, present in the employed FPGA SoC. The resulting approximate 2D DCT utilizes only 1435 logic elements and 771 one-bit registers, 34.32%, and 54.11% of reduction, compared to the exact transform counterpart that we also implemented. In terms of clock cycle count, the proposed accelerator reduces by 96% compared to a single-core RISC-V with a 5-stage pipeline.