A 1pJ/bit Bypass-SPI Interconnect Bus with I2C Conversion Capability and 2.3nW Standby Power for Fabric Sensing Networks

Enabling self-powered in-fiber or in-textile sensing systems necessitates the development of a compact, highly expandable, and ultra-low-power (ULP) communication protocol. This work presents an ULP "bypass-SPI" chip-to-chip interconnect bus designed specifically for fabric-based network communication, requiring only a fixed set of four wires. This interconnect bus allows the chips to bypass the interconnect signals to the downstream chips using a dedicated bypass procedure, facilitating small form factors. A voltage and direction controller is integrated on-chip, which allows the expansion of interconnect signals in multiple directions, supporting mesh-style distributed fiber networks and enabling voltage shifting. Moreover, this interconnect bus is synthesizable, compatible with the standard SPI interfaces, and can be converted into an I
²
C protocol, significantly improving its flexibility. Fabricated in 65nm CMOS technology, measurements of the chip show that the chip achieves a minimum standby power of 2.3 nW and reduces the energy per cycle by over 17× down to 1 pJ/bit, compared to prior art. The communication between bypass-SPI chips and a RISC-V SoC is also measured, confirming the suitability of this interconnect bus for energy-and-space-constrained fabric-based sensing applications.