Optimum Position of Digital DAC Error Correction relative to the Decimation Filter in ΔΣ ADCs

This paper investigates the interaction of digital DAC correction in multibit Delta-Sigma-Modulator (DSM) in combination with a state of the art (SoA) decimation filter. A wide-band continuous-time (CT-)DSM is used as an exemplary architecture for simulation. The presented work provides information about the behaviour of the bit widths of different decimation filter stages and relates them to each other with regard to their frequency and filter-order within a case study. In contrast to prior art, not only the trivial correction positions before and after the decimation filter are considered, but also the options within a Cascaded Integrator-Comb (CIC)-chain are evaluated. A surprising finding is that the optimum for the position of a digital DAC correction lies within the CIC-chain in the chosen case study. The proposed correction restores the DSM to 59 dB consistently, compared to (worst-case) 47 dB before the correction, whereas the correction doubles the decimation-filters power-consumption This work closes part of the gap between published dynamic-error DAC correction techniques and their implementation, and it provides information on what such a correction costs in relation to a decimation filter.