Design of an 20 GHz Wide-Band Input Buffer

With the communication speed requirements growing more rapidly than the technology is advancing, new and enhanced ADCs have to be developed to ensure the required performance. Thereafter, this work investigates several different input buffers (IBs) for direct-conversion ADCs, implemented in a 7 nm FinFET technology. To achieve a thorough analysis of the concepts, the study begins with exploration of promising single-stage topologies in thick-gate devices. It was found that, single-stage design lacks in several performance aspects. Hence, bandwidth (BW) extension techniques as T-coil with series peaking and distributed approach are applied to ensure high enough BW to meet the requirements. Lastly, a two-stage IB topology with thick-oxide devices together with thin-oxide devices is designed to obtain full analysis of relevant study cases. The proposed architecture exhibits 20 GHz of BW with a linearity (IM3) higher than 40.1 dBc, and a DC power dissipation lower than 63.6 mW without compromising reliability and robustness.