Implementation of a Hardware Accelerated VVC Decoder on ARM and FPGA

This paper presents a hardware accelerated implementation of a complete Versatile Video Coding (VVC) video decoder on an Arty Z7-20 FPGA board. In this work, we have ported the original C++ source code, released as open source by Fraunhofer Institute, to the Processing System (PS) of the FPGA board which includes an ARM Cortex A9 processor. On the other hand, we implemented the 8-point and 16-point IDCT-II functions as Programmable Logic (PL) on the FPGA. The communication between the PS and the PL was realized via DMA. Furthermore, we designed the necessary hardware for the HDMI output to display the decoded frames on a monitor. According to the tests that were carried out using a sample stream, hardware accelerated IDCT functions on FPGA run about 20 times faster compared to their software counterparts on ARM.