FPGA Based Intelligent Hardware Trojan Design and its SoC Implementation

Complex microprocessor-based digital embedded systems are typically composed of several third-party Intellectual Property (IP) cores. There is a possibility that IP cores obtained from different sources contain hardware trojans that could leak information for different purposes. In this paper, we have proposed a Hardware Trojan (HT) that can covertly sniff the interconnect bus to detect encrypted data streams. The HT, hidden in the Wishbone Interconnect, intelligently detects and identifies the specific IP core that is sending an encrypted data stream to the processor. The HT has been designed using a Multi-Layer Perceptron (MLP) based approach. After detecting an encrypted data stream, the HT determines the address of the originating peripheral. To demonstrate a fully functional System on Chip (SoC), a RISC-V core interconnected with several peripheral IP cores such as Advanced Encryption Standard (AES), Universal Asynchronous Receiver Transmitter (UART), Serial Peripheral Interface (SPI), and Inter-Integrated Circuit $(\mathrm{I}^{2}\mathrm{C})$ protocols was developed. A Nexys A7 board with Artix-7 FPGA was used for prototyping. The output of the HT has been observed and verified using Vivado Integrated Logic Analyzer IP. The developed IP core of bus-based HT can be used to minimize the risk of data leakage at the early design and prototyping stage in a high-end embedded application.