Efficient Co-Design Methodology combinig Fast and Accurate System-level Simulations with Transistor-level Characterization

The Charge-Pump PLL (CP-PLL) stays one of the most popular circuit topologies used for frequency synthesis. Because of its mixed-signal nature, no established linear theory allows an exact description of its behavior, making its design challenging. In this paper an efficient design approach of the CP-PLL is presented achieving accuracy and time efficiency while considering nonlinear and non-ideal effects. A very efficient event-driven simulation model is combined with a CMOS-based design approach. The extracted macroscopic parameters are used at the behavioral level in order to allow a very fast but accurate closed-loop simulation, leading to a robust top-down and bottom-up co-design methodology.