Reduced GaN Half-Bridge IC Switching Loss on Biased Si p-n Junctions

Substrate-biasing effects in monolithic GaN half-bridge ICs are suppressed on Si substrates with pn junction isolation and local buried substrate-to-source terminations, similar to GaN-on-SOI. However, the vertical depletion capacitances of the p-n junctions add to the switch-node capacitance (in contrast to discrete half-bridges) and slightly increase switching times, losses and energies. This work’s approach is to intentionally bias the substrate towards negative voltages to reduce the effective vertical depletion capacitance. After C-V and I-V characterization of the vertical Si p-n junction in a commercial GaN half-bridge IC, experimentally a switching loss reduction of up to −6% at 1 MHz,32 V switching is demonstrated by applying up to −40 V average substrate voltage via a LR-type bias tee. The work provides insight into p-n junction isolation for monolithic GaN power converter ICs.