Wideband N-Path-Based Phased-Array Receiver With Gain and Phase Mismatch Calibration

This article presents a wideband
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-path-based phased-array receiver capable of interference suppression in both frequency and spatial domains. Spatial-domain filtering is realized by adjusting a time shift in clock signals while interferers located at the undesired harmonics of the clock frequency are rejected through a harmonic recombination network. The elimination of power-consuming phase shifters and their large area in this work results in a compact and power-efficient design with adaptive-beamforming capability. Moreover, the impacts of mismatches between different paths are investigated and a calibration scheme is presented to achieve accurate beamforming and improved harmonic rejection for wideband applications. To demonstrate the feasibility of the presented concept, a four-element prototype is realized in 65-nm CMOS technology with an active area of 0.45 mm 2 and a beamforming accuracy of 3-bit. The fabricated chip covers the 1.0–4.0 GHz frequency range with a maximum single-element conversion gain of 22.3–25.4 dB with 4-bit gain control. At the maximum gain setting, the receiver has a single-element noise figure (NF) of < 5.5 dB and an in-band/beam input third-order intercept point (IIP3) of better than −9.8 dBm over the RF range. The third harmonic rejection ratio (HRR3) is larger than 53 dB, owing to the proposed calibration scheme. The measured array patterns illustrate a peak-to-null ratio of over 26 dB and an error vector magnitude (EVM) of −24.2 dB is obtained for a 64-QAM signal in the presence of a strong spatial in-channel interferer. The total power consumption of the chip is less than 106 mW from a 1.2-V supply voltage.