An External Cap-Less LDO with Low Noise and High Power Supply Rejection

This paper proposes a low output noise, high power supply rejection (PSR) external cap-less low-dropout regulator (LDO). The proposed LDO adopts two-stage cascaded power transistors to improve the PSR, and the output noise is optimized by simultaneously using a first-stage low noise error amplifier (EA) and a low-pass RC filter, thus suppressing the first stage LDO noise and filtering out the reference voltage. Additionally, a P-type flipped voltage follower (FVF) and transient improvement circuits are employed to enhance the transient response capability. The proposed LDO achieves a PSR of -63dB at 1MHz, an output noise of 2.7nV/sqrt(Hz) at 1MHz, an integrated output noise of 6.53πVRMS from 1kHz to 1MHz, and the undershoot/overshoot of 195mV/246mV.