A 94-GHz Down-Conversion Mixer with 15.8-dBm IIP3 Based on Multiple-Gate Transistor Structure

This paper presents a 94 GHz down-conversion mixer with high linearity in a 40-nm CMOS process. A multiple-gate transistor (MGTR) structure is used in the g
m
stage of the Gilbert cell to improve its linearity. In addition, a PMOS cross-coupled pair is adopted for providing negative impedance and current bleeding. Meanwhile, a coupled line based matching network is introduced between the g
m
stage and the switch stage to resonate parasitic capacitance and improve the noise and gain performance. The proposed mixer exhibits a conversion gain of 2.4 dB and a NF of 16.3 dB. The simulated IIP
3
is 15.8 dBm and IP
1dB
is −3.8 dBm. The mixer draws 11.3 mA from a 1.1 V supply voltage excluding the LO buffer which consumes DC power of 14.5 mW.