Fast Parallel Multiple Access Distributed Arithmetic (FPMA-DA) Reconfigurable FIR Filter

A finite impulse response (FIR) filter is an influential block in various signal processing applications. The complexity in VLSI implementation of FIR filters is dominated by the number of multiply and accumulate (MAC) operations. Distributed Arithmetic (DA) is an alternative technique where the $MAC$ operations can be replaced by a series of memory elements and addition operations. FIR filters based on DA are computationally efficient because of the high degree of mechanization involved in the implementation of MAC operations using DA. Many reconfigurable and non reconfigurable FIR filter architectures can be developed using DA. This paper reviews the direct FIR filter implementation and compares it to the existing FIR filter architectures based on DA and the proposed fast parallel multiple access FPMA DA FIR filter different architectures. The FPMA DA FIR filter can achieve $ 26\%$ better than direct implementation in terms of power consumption numbers and $36\%$ better in terms of area numbers at high computation complexity, and can operate at a maximum frequency 120MHz higher than the direct FIR filter implementation.