Verilog-A Model of a SAR-Based Capacitance-to-Digital Converter for Sensor Applications

This paper presents a system-level Verilog-A model for an 8-bit successive approximation register (SAR) capacitance-to-digital converter (CDC). The Verilog-A model provides fast simulation results reducing both simulation time and computational power compared to transistor-level simulations. The model can be used in circuit simulations to capture the ideal system behavior for a suitable top-bottom design approach. The model is simulated in both time and frequency domains using Cadence Virtuoso design tool. The simulations prove the system has an SQNR of 48.9 dB and an ENOB of 7.84 bits.