A Post-Silicon Validation Method for Low-Power 180 nm Dynamic Comparator in Differential 10-bit SAR ADC

The actual performance of the low-power dynamic comparator in quantizing the LSB of 10-bit SAR ADC differentiation is verified from post-silicon measurement results. In post-silicon measurement requires an optimised PCB testing board to measure the fabricated 10-bit SAR ADC. In low voltage design, additional parasitic induced in the PCB test board will degrade the signal quality, especially in voltage-limited headroom comparator circuits. The main objective of this research is to develop an optimised PCB test board for measuring the post-silicon comparator in 10-bit SAR ADC. Physical SAR ADC design measurements are performed using standard ADC testing methods with 2 MHz clock sampling and VDD 1.8 V for the SAR Logic block, VDDA = 0.8 V for the comparator and DAC blocks. The measurement results of the SAR ADC fabricated chips proved the proposed double-tail dynamic comparator's ability to compare the LSB while generating full 10-bit codes without missing code. The measurements of the performance on the SAR ADC also prove that the proposed comparator has successfully achieved 0.9LSB DNL and an ENOB of 8.2 bits.