Efficient and High Performance Ternary SRAM

In every application static random access memory is used for high speed register , cache and relatively small memory banks such as a frame buffer in the increased demand of SRAM with large use in system on-chip . It stores information in the form of binary values due to this reason it require more number of cells. Nowadays, ternary logic is popularly used and It is the best substitute for traditional binary logic because of its storage capacity and delay that results from reduced degree of complexity in interconnects and chip area. This project proposes the design of standard ternary inverter, by arranging ternary standard inverters back to back a Trit storage element is implemented as a ternary SRAM cell and continuous read operation is obtained by Transmission gate technology. We measure the performance by considering the parameters area, delay and power. Tanner T- spice based circuit simulation of the proposed designs were carried out, Simulation result demonstrates an increased performance of area and delay for the Proposed design as compared to the existing design.