Heterogeneous Chiplet Solution for Non-volatile In-memory Computing Architecture

In order to overcome the memory wall problem, academia and industry have proposed AI accelerator architecture based on non-volatile in-memory computing (IMC) devices. However, this computing architecture has a low utilization rate of hardware resources, resulting in a large amount of buffer and memory computing device resource waste. Therefore, in order to better compatible with traditional convolutional neural networks and improve the utilization of hardware resources, this paper proposes a heterogeneous chiplet solution. This solution tries to meet the requirements of the size and depth of the feature map of different layers in the same convolutional neural network model for hardware resources, and greatly increases the utilization rate of hardware resources. Compared with the homogeneous solution, this solution improves the utilization rate of buffer resources by more than 50 %, and the increase of latency can be ignored.